1. Technical Field
The present invention relates to an electronic device comprising at least one chip enclosed in a package.
2. Description of the Related Art
As it is well known, the present and more recent electronic devices, in particular for power applications, are the result of innovations relating both silicon (chip) and package.
Generally described, an electronic device normally comprises a chip, which is the core of the device and a package, which is used with the aim of protecting the chip. In particular, the package is also configured to ensure that electrical connections of the chip itself can be accessed from the outside, such for a PCB (acronym from the English: “Printed Circuit Board”) whereon the final device is mounted.
The electrical contacts of the chip, usually indicated as electrodes, are then brought back on external pins or leads of the package through suitable interconnections realized with conductive materials, such as metallic, among which, gold, copper or aluminum, to name a few.
Among the various factors that have led and continue to lead the evolution of the electronic devices the following ones, for example, are significant:
the desire for reducing the area of the PCBs, in particular in portable applications, that pushes towards electronic devices being less bulky, such as having a low thickness and a reduced weight; and
the desire for improving the global electrical performances of these electronic devices, that can be heavily downgraded by the package and in particular by the specific interconnections for making the electric contacts of the chip comprised therein available from the outside of the package through the pins.
Several efforts have been already made for realizing more compact chips with the functions performed remaining the same, so as to reduce the total space of the electronic device that comprises them. The capacity of realizing this type of compact chips is linked to the new technologies of diffusion on silicon (photolithographic processes etc.) that allow for greater packaging density.
Considering for example the well known power metal-oxide-semiconductor (MOS) devices, commonly indicated as PowerMOSFET, the evolution of the photolithographic technologies has allowed to switch from the tenth of millions of equivalent cells/inch2 of the beginning of the century up to the present hundred of millions of equivalent cells/inch2.
Obviously, the miniaturization of the silicon chips is typically accompanied by a corresponding miniaturization of the package that comprises them. In particular, the packages are characterized, as to the dimensional aspects, by the ratio between a maximum value of embedded silicon area (i.e., the area of the chip) and a minimum value of the space desired for the assembly of the package itself on the PCB board, also referred to as a foot print. It is emphasized that this ratio has already been reduced from a value of about 0.3 in the early 1990s, to a present value of about 0.9.
It is evident that the value of this ratio of areas is strongly influenced also by the techniques of interconnection between chip and package that request to allocate suitable space inside the package itself. Electric interconnections are generally realized by means of wires of conductive material (realized in aluminum, gold or copper, for indicating a few of them) or, in the most recent technologies, through metallic ribbons, in particular of aluminum (indicated as “Al Ribbon”) or metallic clips, in particular of copper (indicated as “Copper clip or bridge”), shown hereafter in greater detail.
It is emphasized that exactly these interconnections can in reality be responsible for possible degradations of the electrical performances of the electronic device as a whole. Considering still by way of an example the PowerMOSFET devices, a single wire of 2 mils (being the mil a unity of length of the English system particularly used in the electrotechnical engineering for the sections of the conductors, equal to 1/1000 of inch and thus to 25.4 μm) of gold (material widely used in the industry of semiconductors) introduces a contribution of about 20 milliOhm on the total resistance value at the turn on or ON resistance of a typical PowerMOSFET device.
Considering that there exist power electronic devices currently manufactured with a total ON resistance of about 1 milliOhm (including the contribution of the silicon chip and of the package) there is a desire for realizing the metallic interconnections by using several metallic wires, in particular bonding wires, in a parallel configuration so as to reduce the parasite components introduced by the package by virtue of these interconnections and thus its contribution to the total ON resistance of the device as a whole.
An example of a configuration of bonding wires in parallel is schematically shown in FIG. 1. In particular, this figure shows an electronic device 10 comprising a chip 12 enclosed by a package 13 provided with a plurality of contact regions 14. Respective pluralities of contact points, 15 and 16, realized on the chip 12 and on the contact regions 14 of the package 13, respectively, are connected by means of bonding wires 17.
From the configuration shown in FIG. 1, it is evident that the bonding wires 17, besides contributing to the potential decay of the electric performances of the electronic device 10 as a whole, are also a limit in the reduction of the global thickness of the package 13 that has to contain them, also due to the geometry necessary to avoid contact between these wires and the edge of the chip.
For improving the performance of the electric interconnections between chip and package, it is also known to use the so called metallic clip technique, for example in Copper or “copper clip”, schematically shown in FIG. 2.
According to this metallic clip technique, an electronic device 20 comprises a chip 22 enclosed in a package 23, in turn provided with a metallic structure or leadframe 28, in particular of copper, which comprises at least one portion 28A whereon the chip 22 is laid, for example with the interposition of a first layer of solder alloy 29A.
The electronic device 20 also comprises a metallic clip 21, for example in copper, solidarized or united by means of interposition of a second layer of solder alloy 29B onto a further portion 28B of the leadframe 28, separated with respect to the portion 28A whereto the chip 20 is united. In particular, the metallic clip 21 has a substantially inverted L shape and is united also to the chip 22 by means of a third layer of solder alloy 29C.
Alternatively, it is possible to use, in place of the metallic clip 21, so called metallic ribbons, for example of aluminum, also suitably connected between the front of the chip and a portion of the leadframe separated with respect to a further portion whereto the chip is united.
At present there are also electronic devices available provided with a package of very reduced size. For example, in the family of the QFN (acronym of: “Quad-Flat No-Leads”) or DFN (acronym of: “Dual Flat No Lead”) packages it is possible to realize electronic devices with total thicknesses lower than 0.4 mm. In this case, the package is suitably provided with at least one planar leadframe that realizes its substrate and a plurality of peripheral regions that allow the connection of the package to the PCB board. These packages can be also provided with an exposed thermal region for facilitating the transfer of heat outside the package itself.
Besides the problems linked to the miniaturization and to the performances above shown for the electronic devices housed in package, it is also to be emphasized that, in the case of power applications, the most recent devices introduce further design complications linked to the vertical conduction of the current that is realized therein.
In fact, a vertical power device comprises, besides one or more electrodes arranged on a first face thereof, indicated for example as front of the device, also at least one electrode arranged on a second and opposite face thereof, indicated as back of the device.
In the case of a vertical conduction PowerMOSFET device, usually the drain contact is placed on the back, while the gate and source contacts are on the front.
For improving the electric performances of the device, minimizing the interconnections between silicon and package, it is thus desired to succeed in efficiently bringing all the contacts (in particular the drain contact in the case of a vertical PowerMOSFET device) back on a same face or surface of the device itself, everything without excessively damaging the electric performances of the chip comprised therein.
It is thus possible, also for vertical conduction devices, to use packages of reduced size, such as for example the FCOL package (acronym of “Flip Chip On Lead-frame”) wherein the chip is assembled so as to have all the contact terminals faced towards a leadframe of the package itself, as schematically shown in FIG. 3. In particular, an electronic device 30 is shown comprising a chip 32 enclosed by a package 33. The chip 32 comprises contacts on one face 34A thereof and is housed in the package 33 with this face 34A faced towards a leadframe 38 also comprised in the package 33. Ball grids or bumps 37 are used for realizing the electric contact between the terminals of the chip 32 arranged on its face 34A and at least one first 38A and one second portion 38B of the leadframe 38.
Packages like FCOL packages, due to the absence of wires for the interconnections between chip and package, allow for maximizing the ratio of areas between “chip size” and “package footprint” having almost equal values, close to 1.
As said, the use of these packages with excellent ratios of areas in the case of vertical conduction devices, in particular vertical power devices, is tied to an efficient configuration of its contacts, in particular to the possibility of bringing back onto the front of the chip the contacts placed on the back.
A known solution for bringing the drain electrode back to the same level of the source and gate electrodes of a PowerMOSFET device is the so called “package oriented” solution, schematically shown in FIG. 4.
In particular, this figure shows an electronic device 40, in particular a vertical conduction power device, comprising a chip 42 enclosed in a package 43, in turn provided with a leadframe 48 whereon the chip 42 is laid, in particular with the interposition of at least one first layer of solder alloy 49A1 and a second layer of solder alloy 49A2. More in particular, the first layer of solder alloy 49A1 is placed in correspondence with a gate contact while the second layer of solder alloy 49A2 is placed in correspondence with a source contact, both realized on a first face 44A of the chip 42. A drain contact is instead realized on a second and opposite face 44B of the chip 42.
The electronic device 40 thus comprises a metallic bridge structure 41 having at least one substantially planar portion 41A, placed in contact with the second face 44B of the chip 42 and united to it by means of a third layer of solder alloy 49C. The metallic bridge structure 41 is also provided with respective wings 41B1 and 41B2 that start from the substantially planar portion 41A and go down to the leadframe 48 from opposite positions with respect to the chip 42; the wings 41B1 and 41B2 are also united to the leadframe 48 by means of a fourth layer of solder alloy 49B1 and a fifth layer of solder alloy 49B2, respectively. In this way, the metallic bridge structure 41 substantially takes the shape of an inverted C wherein the chip 42 is placed and realizes the connection of the drain contact placed on its second face 44B to the leadframe 48, bringing in this way all the contacts of the chip 42 to the level of the leadframe 48.
It is also possible, alternatively, still in the case of a vertical conduction power device, to use a so called “die oriented” solution, in which metal or silicon sinkers are used for bringing the drain contact placed on the back of the chip back on its front. Solutions of this type are described for example in US patent applications No. 2008/0142883 published on Jun. 19, 2008 and No. 2006/0071242 published on Apr. 6, 2006.
These solutions utilize, however, the realization of suitable structures inside the chip able to bring all its contacts, in particular the gate, source and drain contacts for a vertical conduction power device such as a PowerMOSFET, back on a same face of the chip itself.
One or more embodiments of the present disclosure is directed a particular configuration of a device comprising at least one chip encapsulated in a package, in particular a vertical conduction power device, having such structural and functional features as to allow for efficiently and simply bringing an electrode placed on a face of the chip, for example a drain contact placed on the back of the chip, back on an opposite face whereon there are other contacts, for example the gate and source contacts placed on the front of the chip, overcoming one or more of the limits and drawbacks affecting the devices as described above.